1. Field of the Invention
The present invention relates to a semiconductor device manufacturing process diagnosis system for use in diagnoses of a manufacturing process during semiconductor manufacture and, more particularly, to a semiconductor device manufacturing process diagnosis system suitable for diagnoses of a manufacturing process of a logic LSI (Large Scale Integrated Circuit) composed of a plurality of logic circuit blocks and a diagnosis method thereof.
2. Description of the Related Art
In an LSI manufacturing line, there exists an LSI for line-monitoring for measuring and analyzing electrical characteristics of an LSI chip to be manufactured and then making the results into statistics for the purpose of improving a yield of LSIs to be manufactured. Strict examination of an electrically abnormal part within a logic LSI whose representative is an ASIC (Application Specific IC) requires a great number of steps and enormous costs. Under these circumstances, used in a conventional logic LSI manufacturing line as a line-monitoring LSI, for example, is such an LSI called TEG (Test Elementary Groups) whose analysis is easy as recited in Japanese Patent Laying-Open (Kokai) No. Heisei 7-14900, and in a line coexisting with memory, used is such a memory LSI as recited in Japanese Patent Laying-Open (Kokai) No. Heisei 9-232388.
FIG. 17 is a diagram showing one example of structure of an LSI for TEG. As illustrated in the figure, an LSI for TEG is constituted by n-stage tree structure of inverter circuits, where 2.sup.(n-1) of output terminals OUT1 OUTm-1 exist for one input terminal IN. Then, based on occurrence conditions of logic abnormality output to the output terminals OUT1.about.OUTm-1, a failing part can be identified and then based on data obtained by visual inspection, identification can be made of the failing part as abnormality caused by a particle found by the visual inspection or by pattern defect (killer defect).
On the other hand, memory LSI is allowed to extract a failing storage element based on electrical characteristics. Then, a failing mode can be presumed with ease based on defective electrical characteristics because a large part of a chip (more than 80%) is occupied by storage elements. Moreover, in memory LSI production, since a few kinds are produced in quantities, it is possible to statistically grasp variation of a yield of LSIs of a kind for a long period of time. This enables optimum line-monitoring.
Since memory LSI has conventionally played a leading role in LSI technologies, monitoring a memory LSI of advanced technology can obtain representative data.
In recent years, however, there is a tendency for a logic LSI whose representative is ASIC to be a kind which plays a leading role in LSI technologies. In addition, it has become a common practice to use dedicated manufacturing lines, so that on a logic LSI manufacturing line, only logic LSIs are manufactured. As a result, the above-described conventional line-monitoring techniques have the following shortcomings.
Because LSIs vary in electric circuit structure according to their kinds, using an LSI for TEG as a line-monitoring LSI does not always lead to detection of a failure characteristic of each type and is therefore not practical. Moreover, even if an LSI for TEG is used for line-monitoring, the LSI for TEG manufactured for line-monitoring does not make a profit, resulting in increase in costs of logic LSI manufactured.
Using a memory LSI as a line-monitoring LSI does not always extract a problem characteristic of a logic LSI because a logic LSI and a memory LSI slightly differ in manufacturing processes. Manufacturing a logic LSI and a memory LSI on the same manufacturing line, therefore, involves a disadvantage of double management in line management, that is, management of a logic LSI and a memory LSI.
On the other hand, with a logic LSI used as a line-monitoring LSI, simple measurement of electrical characteristics of a logic LSI can not find which part of the logic LSI has a failure. It is therefore impossible to correlate a visually abnormal part and a failing part of a circuit. As a result, using a logic LSI as a line-monitoring LSI is also difficult.
As conventional software for discriminating a failing part of an LSI, there are, as illustrated in FIG. 18, software employing a system called reverse logic development in which a failing part is presumed through logical simulation by tracing logic from the output side toward the input side based on output abnormality information and software employing a system called failure dictionary method by which a failure within a circuit is defined and determination is made whether the failure coincides with an output failure through logical simulation.
None of the methods is, however, practical for use in line-monitoring which requires speediness because volumes of data processing and enormous simulation time are needed (e.g. 100K-gate-class LSI needs data processing of about 5 GB of data and an average of 100 hours of simulation time).